CESAME: A test chip for the validation of a parasitic emission prediction flow in 0.18μm CMOS technology

IEEE International Symposium on Electromagnetic Compatibility

Volumn 2, Issue , 2004, Pages 372-376

  Vrignon, Bertrand ^a   Bendhia, S ^b   Courau, L ^a   Sicard, E ^b,c  

^a STMICROELECTRONICS   (France)

^b INSA   (France)

^c AIRBUS GROUP INNOVATIONS   (Germany)

Author keywords

CMOS; EMC; IC design; Parasitic emission

Indexed keywords

ELECTRIC POTENTIAL; ELECTROMAGNETIC COMPATIBILITY; MAGNETOELECTRIC EFFECTS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; SIGNAL INTERFERENCE; SWITCHING;

CURRENT WAVEFORMS; IC DESIGN; PARASITIC EMISSION; VOLTAGE FLUCTUATION;

CMOS INTEGRATED CIRCUITS;

EID: 4644253613     PISSN: 10774076     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. The EDA Roadmap, 2002 Release, www.medeaplus.org
2. IEC 61967: EMC of ICs: Conducted and radiated measurement methods
3. IEC 62014-3: EMC for ICs: An Integrated Circuit Emission model ICEM.
4. S. Baffreau, C. Huet, C. Marot, S. Calvet, E. Sicard, "A Standard Model for predicting the emission of Microcontrollers", Proceedings of the International Conference on Electromagnetic Compatibility, Sorrento, 2002
5. W. John, T. Steinecke, H. Kohne, R. Niebauer "Methodology for EME reduction on Chip level", Proceeding of the IEEE International Symposium on Electromagnetic Compatibility, pp 593-598, 2000
6. MEDEA+ A509 MESDIE Project : www.mesdie.org
7. S.Delmas-Bendhia, F. Caignet S. Sicard, "A new method for measuring signal integrity in CMOS ICs", Microelectronics International, vol. 17, no, 1, pp 17-19, MCB University Press (2000).
8. F. Caignet, S. Delmas-Benddhia, P. Saintot, E. Sicard "The challenge of Signal Integrity in Deep Submicron CMOS technology", IEEE proceedings, April 2001, Vol 89, N°4