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Volumn , Issue , 2006, Pages 785-790
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Shift-or circuit for efficient network intrusion detection pattern matching
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER ARCHITECTURE;
COMPUTER CRIME;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
FUZZY LOGIC;
INTERNET;
NETWORK ARCHITECTURE;
PATTERN MATCHING;
SECURITY OF DATA;
SENSORS;
SHIFT REGISTERS;
CO-PROCESSOR ARCHITECTURE;
EXPERIMENTAL RESULTS;
FIELD PROGRAMMABLE LOGIC (FPL);
FPGA IMPLEMENTATIONS;
INTERNATIONAL CONFERENCES;
NETWORK INTRUSION DETECTION;
NETWORK INTRUSION DETECTION SYSTEM (NIDS);
INTRUSION DETECTION;
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EID: 46249124852
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/FPL.2006.311314 Document Type: Conference Paper |
Times cited : (13)
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References (9)
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