Phase noise reduction in high speed frequency divider

2006 IEEE Dallas/CAS Workshop onDesign, Applications, Integration and Software, DCAS-06

Volumn , Issue , 2006, Pages 83-86

  Prakash, Rahul ^a   Akhtar, Siraj ^b   Balsara, Poras T ^a  

^a UNIVERSITY OF TEXAS AT DALLAS   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

(+ MOD 2N) OPERATION; CARRIER FREQUENCY (VC); DESIGN OPTIMIZATION (DO); FREQUENCY DIVIDER (FD); HIGH SPEED FREQUENCY DIVIDER; HIGH-FREQUENCY (HF); INPUT FREQUENCY; LOW-PHASE-NOISE; MAXIMUM OPERATING FREQUENCY (FMAX); NOISE CHARACTERISTICS; NOISE LEVELS; NOMINAL FREQUENCY; OPTIMIZATION PROCESSES; PHASE NOISE REDUCTION; POWER CONSUMPTION (CE);

DIGITAL SIGNAL PROCESSING; FREQUENCY DIVIDING CIRCUITS; OPTIMIZATION; PHASE NOISE; PROCESS DESIGN; PROCESS ENGINEERING; SOFTWARE DESIGN;

PHASE BEHAVIOR;

EID: 46249107931     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DCAS.2006.321039     Document Type: Conference Paper

References (5)

1. N. Foroudi and T. A. Kwasniewski, "CMOS High-speed dual-modulus frequency divider for RF frequency synthesis", IEEE JSSC, Feb. 1995.
2. M. Nogawa and Y. Ohtomo, "A 16.3-GHz 64:1 CMOS frequency divider", The second IEEE Asia Pacific Conference on ASICs, Aug. 2000.
3. A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," IEEE Journal of Solid-State Circuits, vol. 33, Feb. 1999
4. J. Phillips and K. Kundert, "Noise in mixers, oscillators and samplers", Proceedings of the IEEE Custom Integrated Circuits Conference, May 2000
5. A. Hajimiri, S. Limotyrakis, and T. H. Lee, "Jitter and phase noise in ring oscillators", IEEE Journal of Solid-State Circuits, vol. 34, June 1999