Accelerating high-level bounded model checking

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 794-801

  Ganai, Malay K ^a   Gupta, Aarti ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; BOOLEAN FUNCTIONS; DESIGN; SCALE (DEPOSITS);

BOUNDED MODEL CHECKING (BMC); COMPUTER-AIDED DESIGN; CONTROLLED EXPERIMENTS; DATA PATHS; HIGH LEVEL DESIGNS; INHERENT LIMITATIONS; INTERNATIONAL CONFERENCES; ON THE FLY (OTF); PERFORMANCE IMPROVEMENTS; PROBLEM FORMULATION; PROBLEM INSTANCES; VERIFICATION MODELS;

MODEL CHECKING;

EID: 46149102489     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320122     Document Type: Conference Paper

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