Guideline for low-temperature-operation technique to extend CMOS scaling

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Hokazono, A ^a   Kawanaka, S ^a   Tsumura, K ^a   Hayashi, Y ^a   Tanimoto, H ^a   Enda, T ^a   Aoki, N ^a   Ohuchi, K ^a   Inaba, S ^a   Okano, K ^a   Fujiwara, M ^a   Morooka, T ^a   Goto, M ^a   Kajita, A ^a   Usui, T ^a   Ishimaru, K ^a   Toyoshima, Y ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CLARIFICATION; COOLING; ELECTRON DEVICES; GATES (TRANSISTOR);

CMOS SCALING; DEVICE DESIGNS; DEVICE OPERATIONS; DEVICE TECHNOLOGIES; HIGH-K GATE DIELECTRICS; LOW TEMPERATURE; LOW TEMPERATURES; OPERATION TEMPERATURES; PROMISING APPROACH; TEMPERATURE RANGES; TOTAL POWER CONSUMPTION;

GATE DIELECTRICS;

EID: 46049115905     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346875     Document Type: Conference Paper

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