A screening methodology for VMIN drift in SRAM arrays with application to sub-65nm nodes

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Ball, M ^a   Rosal, J ^a   McKee, R ^a   Loh, W K ^a   Houston, T ^a   Garcia, R ^a   Raval, J ^a   Li, D ^a   Hollingsworth, R ^a   Gury, R ^a   Eklund, R ^a   Vaccani, J ^a   Castellano, B ^a   Piacibello, F ^a   Ashburn, S ^a   Tsao, A ^a   Krishnan, A ^a   Ondrusek, J ^a   Anderson, T ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

65-NM NODES; AND GATES; INTEGRAL PART; NEGATIVE BIAS TEMPERATURE INSTABILITIES; SRAM ARRAYS; SRAM STABILITY; SYSTEM-ON-CHIP DEVICES;

ELECTRON DEVICES; FIELD EFFECT TRANSISTORS;

STATIC RANDOM ACCESS STORAGE;

EID: 46049113920     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346883     Document Type: Conference Paper

References (4)

1. E. Seevinck, "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE Journal of Solid-State Circuits, Vol. SC-22No. 5, 1987
2. st ed. Gouda, The Netherlands: ComTex, 1991.
3. M. Reidel, "Fault coverage analysis of RAM test algorithms," VLSI Test Symp., 1995, pp.227-234
4. P. Veenstra, F. Beenker, and J. Koomen, "Testing of random access memories: Theory and practice," Proc. IEEE, vol. 135, pt. G, Feb. 1988