Analysis and design of transceiver circuit and inductor layout for inductive inter-chip wireless superconnect

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 246-249

  Miura, Noriyuki ^a   Mizoguchi, Daisuke ^a   Yusof, Yusmeeraz Binti ^a   Sakurai, Takayasu ^b   Kuroda, Tadahiro ^a  

^a KEIO UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

High bandwidth; Inductor; Low power; SiP; Wireless bus

Indexed keywords

BANDWIDTH; BUSBARS; ELECTRIC INDUCTORS; MATHEMATICAL MODELS; OPTIMIZATION; RADIO; SPURIOUS SIGNAL NOISE;

INDUCTOR LAYOUT; LOW POWER; TRANSMIT POWER; WIRELESS BUSES;

TRANSCEIVERS;

EID: 4544359929     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. S. Mick, J. Wilson, P. Franzon, "4Gbps High-Density AC Coupled Interconnection," IEEE Proceedings of CICC, pp.133-140, May 2002.
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5. D. Mizoguchi, Y. B. Yusof, N. Miura, T. Sakurai, and T. Kuroda, "A 1.2Gb/s/pin Wireless Superconnect Based on Inductive Inter-Chip Signaling (US)," to be published in ISSCC 2004.
6. C. C. Tang, C. H. Wu, and S. I. Lin, "Miniature 3-D Inductors in Standard CMOS Process," IEEE Journal of Solid-State Circuits, vol.37, no.4, pp.471-478, April 2002.