A ∑-Δ fractional-N synthesizer with a fully-integrated loop filter for a GSM/GPRS direct-conversion transceiver

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 42-45

  Hwang, In Chul ^a   Lee, Han Il ^b   Lee, Kun Seok ^a   Cho, Je Kwang ^a   Nah, Kyung Suc ^a   Park, Byeong Ha ^a  

^a SAMSUNG Electronics   (South Korea)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACOUSTIC NOISE; BROADBAND NETWORKS; CMOS INTEGRATED CIRCUITS; FREQUENCIES; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; MICROPROCESSOR CHIPS; TRANSCEIVERS;

ADAPTIVE FREQUENCY CALIBRATION (AFC); GPRS; INTEGRATED LOOP FILTERS; SYNTHESIZERS;

SIGNAL FILTERING AND PREDICTION;

EID: 4544331357     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

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2. A. Hajimiri, and T. H. Lee, "Design issues in CMOS differential LC oscillator," IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, May, 1999.
3. S. Solis-Bustos, J. Silva-Martinez, F. Maloberti, and E. Sanchez-Sinencio," A 60-dB Dynamic-Range CMOS Sixth-Order 2.4-Hz Low-Pass Filter for Medical Applications," IEEE Tran. Circuits and Syst. II, vol. 47, no. 12, Dec. 2000
4. th order S-D modulator," Proc. of ESSCIRC 2002, pp. 803-806.