Introducing a silicone under the bump configuration for stress relief in a wafer level package

Proceedings of 5th Electronics Packaging Technology Conference, EPTC 2003

Volumn , Issue , 2003, Pages 380-384

  Vanden Bulcke, M ^a   Gonzalez, M ^a   Vandevelde, B ^a   Winters, C ^a   Beyne, E ^a   Larson, L ^b   Harkness, B R ^b   Gardner, G ^b   Mohamed, M ^b   Sudbury Holtschlag, J ^b   Meynen, H ^c  

^a IMEC   (Belgium)

^b DOW CORNING CORPORATION   (United States)

^c Dow Corning SA Belgium   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; INTEGRATED CIRCUIT DESIGN; MANUFACTURE; METAL CLEANING; METALLIZING; METALS; MICROELECTRONICS; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT DESIGN; PRINTED CIRCUITS; RELIABILITY; SILICON WAFERS; SILICONES; SOLDERING; STRESS RELIEF; THERMAL EXPANSION; WAFER BONDING;

DEVICE ARCHITECTURES; HIGH VOLUME MANUFACTURING; MANUFACTURING COST; PROCESS REQUIREMENTS; STACKED-CHIP PACKAGE; THERMAL EXPANSION MISMATCH; WAFER LEVEL PACKAGE; WAFER LEVEL PACKAGING;

ELECTRONICS PACKAGING;

EID: 10444269719     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2003.1271550     Document Type: Conference Paper

References (5)

1. th Electronic Components and Technology Conf., New Orleans, LA, May 2003, pp. 857-863.
2. Neng-Hsing, L., "Process Optimization for CF4/O2 Plasma Etch of Silicone Elastomer", MRL Bull. of Res. & Dev., Vol. 5, No. 1 (April 1991), pp. 33-38.
3. Baklanov, M. R. et al, "Effects of Oxygen and Fluorine on the Dry Etch Characteristics of Organic Low-k Dielectrics", J. Vac. Sci. Technol. B, Vol. 17, No. 2 (1999), pp. 372-379.
4. Vitale, S. A. et al, "Etching Chemistry of Benzocyclobutene (BCB) Low-k Dielectric Films in F2 + O2 and C12 + O2 High Density Plasma", J. Vac. Sci. Technol. A, Vol. 18, No. 6 (2000), pp. 2770-2778.
5. Box, G.E.P. and J.S. Hunter., 1978. Statistics for Experimenters, John Wiley & Sons (New York, 1978).