Modeling of chemical-mechanical polishing on patterned wafers as part of integrated topography process simulation

Microelectronic Engineering

Volumn 76, Issue 1-4, 2004, Pages 89-94

  Nguyen, P H ^a   Bar E ^a   Lorenz, J ^a   Ryssel, H ^a,b  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED SYSTEMS AND DEVICE TECHNOLOGY IISB   (Germany)

^b UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

Chemical mechanical polishing; Integrated circuit interconnect; Semiconductor process simulation

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COMPUTER SIMULATION; DEFORMATION; DEPOSITION; ETCHING; MATHEMATICAL MODELS; PARAMETER ESTIMATION; STRESSES;

INTEGRATED CIRCUIT INTERCONNECTS; REMOVAL RATE (RR); SEMICONDUCTOR PROCESS SIMULATION; SHALLOW TRENCH ISOLATION (STI);

SILICON WAFERS;

EID: 4544269235     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2004.07.018     Document Type: Conference Paper

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