Model checking a fault-tolerant startup algorithm: From design exploration to exhaustive fault simulation

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2004, Pages 189-198

  Steiner, Wilfried ^a   Rushby, John ^b   Sorea, Maria ^c   Pfeifer, Holger ^c  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^b SRI INTERNATIONAL   (United States)

^c UNIVERSITY OF ULM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SYSTEM RECOVERY; MATHEMATICAL MODELS; PARAMETER ESTIMATION; TIME DIVISION MULTIPLE ACCESS;

EXHAUSTIVE FAULT SIMULATIONS; FAULT HYPOTHESIS; TIME-TRIGGERED ARCHITECTURE (TTA);

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 4544238775     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dsn.2004.1311889     Document Type: Conference Paper

References (14)

1. A. Ademaj, G. Bauer, H. Sivencrona, and J. Torin. Evaluation of fault handling of the Time-Triggered Architecture with bus and star topology. In Proc. of International Conference on Dependable Systems and Networks (DSN 2003), San Francisco, Jun. 2003.
2. G. Bauer, H. Kopetz, and P. Puschner. Assumption Coverage under Different Failure Modes in the Time-Triggered Architecture. In Proc. of International Conference on Emerging Technologies and Factory Automation, pages 333-341, Oct. 2001.
3. G. Bauer, H. Kopetz, and W. Steiner. The central guardian approach to enforce fault isolation in a time-triggered system. In Proc. of 6th International Symposium on Autonomous Decentralized Systems (ISADS 2003), pages 37-44, Pisa, Italy, Apr. 2003.
4. C. Bernardeschi, A. Fantechi, and S. Gnesi. Model checking fault tolerant systems. Software Testing, Verification and Reliability, 12:251-275, Dec. 2002.
5. L. de Moura, S. Owre, H. Ruess, J. Rushby, N. Shankar, M. Sorea, and A. Tiwari. SAL 2. To be presented at CAV 2004, July 2004. Available at http://www.csl.sri.com/~rushby/abstracts/sal-tool.
6. B. Dutertre and M. Sorea. Timed systems in SAL. Technical report, Computer Science Laboratory, SRI International, Menlo Park, CA, 2004. In preparation.
7. J.C.Laprie. Dependability: Basic Concepts and Terminology. Springer-Verlag, 1992.
8. H. Kopetz. Fault containment and error detection in the Time-Triggered Architecture. In Proc. of The 6th International Symposium on Autonomous Decentralized Systems (ISADS 2003), pages 139-146, Pisa, Italy, Apr. 2003.
9. H. Lönn and P. Pettersson. Formal verification of a TDMA protocol start-up mechanism. In Pacific Rim International Symposium on Fault-Tolerant Systems, pages 235-242, Taipei, Taiwan, Dec. 1997. IEEE Computer Society.
10. H. Pfeifer, D. Schwier, and F. W. von Henke. Formal verification for time-triggered clock synchronization. In C. B. Weinstock and J. Rushby, editors, Dependable Computing for Critical Applications - 7, volume 12 of Dependable Computing and Fault Tolerant Systems, pages 207-226, San Jose, CA, Jan. 1999. IEEE Computer Society.
11. W. Steiner and M. Paulitsch. The transition from asynchronous to synchronous system operation: An approach for distributed fault-tolerant systems. In The 22nd International Conference on Distributed Computing Systems, pages 329-336, Vienna, Austria, July 2002. IEEE Computer Society.
12. W. Steiner, M. Paulitsch, and H. Kopetz. Multiple failure correction in the Time-Triggered Architecture. Proc. of 9th Workshop on Object-oriented Real-time Dependable Systems (WORDS 2003f), Oct. 2003.
13. W. Steiner, J. Rushby, M. Sorea, and H. Pfeifer. SAL model of a TTA startup algorithm. Research Report 52/2003, Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 1-3/182-1, 1040 Vienna, Austria, 2003.
14. T. Yokogawa, T. Tsuchiya, and T. Kikuno. Automatic verification of fault tolerance using model checking. In Proc. of 2001 Pacific Rim International Symposium on Dependable Computing, page 95, Seoul, Korea, Dec. 2001.