A new approach to the modeling of oxide breakdown on CMOS circuits

Microelectronics Reliability

Volumn 44, Issue 9-11 SPEC. ISS., 2004, Pages 1519-1522

  Fernandez R ^a   Rodriguez R ^a   Nafria M ^a   Aymerich, X ^a  

^a UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC POTENTIAL; HARDNESS; MATHEMATICAL MODELS; MOSFET DEVICES; OSCILLATIONS; OSCILLATORS (ELECTRONIC); SHORT CIRCUIT CURRENTS;

CIRCUIT PERFORMANCES; DIELECTRIC BREAKDOWNS; OXIDE BREAKDOWN; VOLTAGE STRESSES;

CMOS INTEGRATED CIRCUITS;

EID: 4544234099     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.07.026     Document Type: Conference Paper

References (7)

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3. Fernández R, Rodríguez R, Nafría M, Aymerich X. DC BD MOSFET model for circuit reliability simulation. Submitted for publication.
4. Sakurai T, Newton AR. A simple MOSFET model for circuit analysis. IEEE Trans. Electron Devices 1991;38(4):887-894.
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6. Rodríguez R, Stathis JH, Linder BP. A model for gate oxide breakdown in CMOS inverters. IEEE Electron Device Lett. 2003; 24 (2):114-116.
7. Degraeve R, Kaczer B, De Keersgieter A, Groeseneken G, Relation between breakdown mode and breakdown location in short channel nMOSFETs and its impact on reliability specifications. IRPS Proc. 2001. p. 360-366.