45 nm CMOS technology with low temperature selective epitaxy of SiGe

Applied Surface Science

Volumn 254, Issue 19, 2008, Pages 6067-6071

  Tamura, Naoyoshi ^a   Shimamune, Yousuke ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Embedded SiGe; Epi temperature; Recess shape; Surface pre treatment

Indexed keywords

CMOS INTEGRATED CIRCUITS; DRAIN CURRENT; EPITAXIAL GROWTH; MOSFET DEVICES; SURFACE CLEANING; SURFACE TREATMENT; TEMPERATURE;

CMOS FABRICATION TECHNOLOGY; EMBEDDED SIGE; RECESS SHAPE; SELECTIVE EPITAXY; SILICON GERMANIUM; SOURCE AND DRAINS; SURFACE CLEANING TREATMENT; SURFACE PRE-TREATMENTS;

SI-GE ALLOYS;

ASSEMBLY; CRYSTALLIZATION; CURRENT DENSITY; GERMANIUM COMPOUNDS; LITHOGRAPHY; SEMICONDUCTOR DEVICES; SILICON COMPOUNDS; SURFACE TREATMENT;

EID: 45049084537     PISSN: 01694332     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.apsusc.2008.02.162     Document Type: Article

References (6)

1. Houghton D.C. J. Appl. Phys. 70 (1991) 2115
2. T. Soeda, Extended abstracts, The 53th Spring Meeting, The Jpn. Soc. Appl. Phys., 2005.
3. Shimamune Y., et al. Proc. Symp. VLSI Technology. Kyoto (2007) 116
4. Ohta H., et al. Tech. Dig. Int. Electron Devices Meet. Washington DC (2005) 247
5. Chopra S., et al. Appl. Phys. Lett. 88 (2007) 202114
6. De Salvador D., et al. Phys. Rev. B 61 19 (2000) 13005