Technological constrains of bulk FinFET structure in comparison with SOI FinFET

2007 International Semiconductor Device Research Symposium, ISDRS

Volumn , Issue , 2007, Pages

  Poljak, Mirko ^a   Jovanović, Vladimir ^b   Suligoj, Tomislav ^a  

^a UNIVERSITY OF ZAGREB   (Croatia)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 44949232320     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2007.4422327     Document Type: Conference Paper

References (3)

1. R. Katsumata, et al., "Fin-Array-FET on bulk silicon for sub-100 nm Trench Capacitor DRAM", VLSI Tech. Dig., pp. 61-62, 2003
2. D. Hisamoto, et al., "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm", IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, 2000
3. Davinci User Guide W-2004.09, Synopsys, Inc., 2004