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A 100-GOPS programmable processor for vehicle vision systems
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IEEE Design & Test of Computers
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Raab, W.1
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Ramacher, U.5
Sauer, C.6
Techmer, A.7
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0344013569
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Real time data association for FastSLAM
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Sept
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Juan Nieto, Jose Guivant, Eduardo Nebot, "Real time data association for FastSLAM," Proceedings of IEEE International Conference on Robotics and Automation, Vol. 1, pp. 412-418, Sept. 2003
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Proceedings of IEEE International Conference on Robotics and Automation
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Nieto, J.1
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3
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A Real-Time Multi Face Detection Technique Using Positive-Negative Lines-of-Face Template
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Aug
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Yuichi Hori, Kenji Shimizu, Yutaka Nakamura and Tadahiro Kuroda, "A Real-Time Multi Face Detection Technique Using Positive-Negative Lines-of-Face Template," Proceedings of International Conference on Pattern Recognition, Vol. 1, pp. 765 - 768, Aug. 2004
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Proceedings of International Conference on Pattern Recognition
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Hori, Y.1
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The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture
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Jan
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Hideyuki Noda, et el., "The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture," IEEE Journal of Solid-State Circuits, Vol. 42, Issue 1, pp. 183 - 192, Jan. 2007
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Noda, H.1
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Object Recognition from Local Scale-Invariant Features
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Lowe, D.G.1
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A 3.84 GIPS integrated memory array processor with 64-processing elements and 2Mb SRAM
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Nov
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A High-Speed Magnitude Comparator With Small Transistor Count
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Dec
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Shun-Wen Cheng, "A High-Speed Magnitude Comparator With Small Transistor Count," IEEE Proceedings of International Conference on Electronics, Circuits and Systems, Vol. 3, Dec. 2003, pp. 1168-1171
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Cheng, S.-W.1
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Solutions for Real Chip Implementation Issues of
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unpublished
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Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seung-Jin Lee, and Hoi-Jun Yoo, "Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC," unpublished.
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Kim, D.1
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