Near fine grain parallel processing using static scheduling on single chip multiprocessors

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn 1999-November, Issue , 1999, Pages 23-31

  Kimura, Keiji ^a   Kasahara, Hironori ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; CACHE MEMORY; COMPUTER ARCHITECTURE; MEMORY ARCHITECTURE; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS;

COARSE GRAINS; DISTRIBUTED SHARED MEMORY; EFFECTIVE PERFORMANCE; INSTRUCTION LEVEL PARALLELISM; PARALLEL PROCESSING; SHARED MEMORY; SINGLE-CHIP MULTIPROCESSORS; STATIC SCHEDULING;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84944409456     PISSN: 15373223     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWIA.1999.898840     Document Type: Conference Paper

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