Flip chip on board: Assessment of reliability in cellular phone application

IEEE Transactions on Components and Packaging Technologies

Volumn 27, Issue 3, 2004, Pages 461-467

  Sillanpää, Markku ^a   Okura, Juscelino Hozumi ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR TELEPHONE SYSTEMS; CHIP SCALE PACKAGES; COMPUTER SIMULATION; FAILURE ANALYSIS; FINITE ELEMENT METHOD; INTEGRATED CIRCUIT TESTING; PRINTED CIRCUIT BOARDS; RELIABILITY; SCANNING ELECTRON MICROSCOPY; SURFACE MOUNT TECHNOLOGY; THERMAL CYCLING;

BALL GRID ARRAY; DIRECT CHIP ATTTACH; INPUT OUTPUT DENSITY; MECHANICAL SHOCK;

FLIP CHIP DEVICES;

EID: 4444374713     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAPT.2004.831767     Document Type: Article

References (15)

1. J. Lau, Low Cost Flip Chip Technologies. New York: McGraw-Hill, 2000.
2. S. Bezuk, "Flip chip challenges," High Density Interconn., pp. 34-40, Feb. 2000.
3. T. A. Nguty and N. N. Ekere, "Chip scale vs. flip chip: issues to consider," Circuits Assembly, pp. 27-32, Nov. 1999.
4. N. Krsmanovic, "Designing the future with bare die," Electron. Packag. Prod., pp. 48-54, July 2000.
5. B. Roesner, "The beneficial effect of underfilling on the reliability of flip chip joints," Solder. Surface Mount Technol., pp. 14-18, May 1998.
6. Ansys GUI Online Help Manual, Canonsburg, PA, 1998.
7. J. H. Lau and Y. H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies. New York: McGraw-Hill, 1997.
8. Ansys Inc., "Lab tests improve accuracy of FEA," ANSYS Solutions, vol. 2, no. 2, Spring 2000.
9. Ansys Inc., "Organizational impact of up-front simulation," ANSYS Solutions, vol. 2, no. 2, Spring 2000.
10. S. Pilz, "Predicting drop impact damage," ANSYS Solutions, vol. 2, no. 3, Summer 2000.
11. W. Lin, "Standard procedure for the simplified board-level drop test simulation," Tech. Rep., Nokia Research Center, Dallas, TX, 2000.
12. W. Lin, Development of a FEM board level model for drop impact simulation, Nokia Research Center, Dallas, TX, 2000.
13. J. Wu, "Global and local coupling analysis for small components in drop simulation," in Proc. 6th Int. LS-DYNA Users Conf., 2000, pp. 11-17-11-26.
14. L. Zhu, "Submodeling technique for BGA reliability analysis of CSP packaging subjected to an impact loading," in Proc. IPACK Conf. Salt Lake City, UT, 2001.
15. J. H. Okura, "effect of temperature and moisture on flip chip on board (FCOB) assemblies," Ph.D. dissertation, Univ. Maryland, College Park, 2000.