RF characterization of ESD protection structures

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2004, Pages 379-382

  Chen, Guang ^a   Feng, Haigang ^a   Xie, Haolu ^a   Zhan, Rouying ^a   Wu, Qiong ^a   Guan, Xiaokang ^a   Wang, Albert ^a   Takasuka, Kaoru ^b   Tamura, Satoru ^b   Wang, Zhihua ^c   Zhang, Chun ^c  

^a ILLINOIS INSTITUTE OF TECHNOLOGY   (United States)

^b Asahi Kasei EMD   (Japan)

^c NONE

Author keywords

Diode string; Electrostatic discharge; ESD protection; Parasitic capacitance; SCR

Indexed keywords

DIODE STRING; ELECTROSTATIC DISCHARGE (ESD); ESD PROTECTION; PARASITIC CAPACITANCE;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC DISCHARGES; MOSFET DEVICES; OPTIMIZATION; SEMICONDUCTOR JUNCTIONS; THYRISTORS;

ELECTROSTATICS;

EID: 4444374571     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A. Wang, On-Chip ESD Protection for Integrated Circuits - An IC Design Perspective, Kluwer Academic Publishers, Boston, 2002, ISBN: 0-7923-7647-1.
2. A. Wang, et al, Proc. IEEE CICC, pp.411-418, 2002.
3. G. Chen, et al, Proc. IEEE RFIC Symp., pp. 347-350, 2003.
4. S. Hyvonen, et al, "Cancellation Technique to Provide ESD Protection for Multi-GHz RF Inputs", Electronics Lett., Vol. 39, No. 3, pp. 284-285, Feb., 2003.
5. P. Leroux, et al, "A 0.8dB NF ESD Protected 9mW CMOS LNA Operating at 1.23GHz", IEEE JSSC, Vol. 37, No. 6, pp. 760-765, June 2002.
6. A. Wang, et al, IEEE Trans. Elec. Devices, Vol. 48, No. 5, pp.978-984, May 2001.