Design optimizations for microprocessors at low temperature

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 2-5

  Vassighi, Arman ^a   Keshavarzi, Ali ^a   Narendra, Siva ^a   Schrom, Gerhard ^a   Ye, Yibin ^a   Lee, Seri ^b   Chrysler, Greg ^b   Sachdev, Manoj ^c   De, Vivek ^a  

^a Circuits Research   (United States)

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF WATERLOO   (Canada)

Author keywords

CMOS; Cooling; Electrothermal modeling; Frequency; Low temperature; Microprocessor; Power; Refrigeration

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COOLING; LOW TEMPERATURE EFFECTS; OPTIMIZATION; REFRIGERATION; TRANSISTORS;

CMOS; ELECTROTHERMAL MODELING; FREQUENCY; LOW TEMPERATURE; MICROPROCESSOR; POWER;

MICROPROCESSOR CHIPS;

EID: 4444314735     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996570     Document Type: Conference Paper

References (4)

1. I. Aller, et. al., 2000 ISSCC, pp. 214-215.
2. K. Banerjee, L. Sheng-Chih, A. Keshavarzi, S. Narendra, V. De, 2003 IEDM, pp. 36.7.1-36.7.4.
3. A. Vassighi, O. Semenov, M. Sachdev, "Thermal Runaway Avoidance", 2004 IRPS.
4. S. Narendra., V. De, S. Borkar, D. A. Antoniadis, A.P. Chandrakasan, IEEE Journal of Solid-State Circuits, March 2004, pp. 501-510.