Fast and accurate parasitic capacitance models for layout-aware synthesis of analog circuits

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 145-150

  Agarwal, Anuradha ^a   Sampath, Hemanth ^a   Yelamanchili, Veena ^a   Vemuri, Ranga ^a  

^a University of Cincinnati   (United States)

Author keywords

Analog Synthesis; Layout Aware; Parasitic Estimation

Indexed keywords

ANALOG SYNTHESIS; CIRCUIT DESIGN; LAYOUT AWARE; PARASITIC ESTIMATION;

AUTOMATION; CAPACITANCE; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTERPOLATION; NEURAL NETWORKS; OPTIMIZATION;

NETWORKS (CIRCUITS);

EID: 4444311838     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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