Simulation of PWB warpage during fabrication and due to reflow

Thermomechanical Phenomena in Electronic Systems -Proceedings of the Intersociety Conference

Volumn 2, Issue , 2004, Pages 674-678

  Halvi, Ananth Srivatsav ^a   Ahn, Wonkee ^a   Agonafer, Dereje ^a   Novotny, Shlomo ^b  

^a Woolf Hall   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

CTE; Layup; Multi layer PWB; Reflow; Warpage

Indexed keywords

LAYUP; MULTI LAYER PWB; REFLOW; WARPAGE;

COMPUTER SIMULATION; COST EFFECTIVENESS; DIELECTRIC MATERIALS; ELECTRIC INDUSTRY; ELECTRONICS PACKAGING; FABRICATION; FINITE ELEMENT METHOD; PROBLEM SOLVING; THERMAL EXPANSION;

PRINTED CIRCUIT BOARDS;

EID: 4444305754     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. The Impact of Board Layout and Layup on PWB Warpage during fabrication and due to Reflow Solder Process: A Review of Literature, proceedings of IPACK 2003.
2. The Impact of Board Layout and stack-up on PWB Warpage During Fabrication and Reflow Soldering Process, Wonkee Ahn and Dr. Dereje Agonafer, UTA-SUN project report, August 04, 2003.
3. Ume, I.C., Martin, T., "Finite Element Analysis of OWN Warpage due cured Solder Mask sensitivity Analysis", IEEE Trans. on Comp. Packaging and Manuf. Tech., Part A, Vol. 20, No.3, pp. 307-316,1997.
4. Yeh, C.P., "An integrated information framework for multidisciplinary PWB design", Ph.D dissertation, Georgia Tech, 1992.