Template design for cellular nonlinear networks with 1-bit weights

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 3, 2008, Pages 904-913

  Laiho, Mika ^a,b   Paasio, Ari ^a   Flak, Jacek ^b   Halonen, Kari A I ^c  

^a UNIVERSITY OF TURKU   (Finland)

^b AALTO UNIVERSITY   (Finland)

^c VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

Author keywords

Analog processing circuits; Cellular neural networks (CNNs); Image processing; Parallel architectures; Threshold logic

Indexed keywords

ALGORITHMS; ANALOG CIRCUITS; DATA PROCESSING; IMAGE PROCESSING; MATHEMATICAL MODELS; THRESHOLD LOGIC;

ANALOG PROCESSING CIRCUITS; CELLULAR NONLINEAR NETWORKS; ONE-BIT WEIGHT; PARALLEL ARCHITECTURES; TEMPLATE DESIGN;

CELLULAR NEURAL NETWORKS;

EID: 44349139527     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.916438     Document Type: Article

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