Design and evaluation of a hardware/software FPGA-based system for fast image processing

Microprocessors and Microsystems

Volumn 32, Issue 2, 2008, Pages 95-106

  Kalomiros, J A ^a   Lygouras, J ^b  

^a TECHNOLOGICAL EDUCATIONAL INSTITUTE OF SERRES   (Greece)

^b Polytechnic School of Xanthi   (Greece)

Author keywords

Embedded processor; FPGA; Hardware software co design; Image processing

Indexed keywords

CHANNEL ESTIMATION; COMMUNICATION SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAM PROCESSORS;

EMBEDDED PROCESSORS; SOFTWARE LOGIC;

IMAGE PROCESSING;

EID: 43449119217     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2007.09.001     Document Type: Article

References (29)

1. W.J. MacLean, An evaluation of the suitability of FPGAs for embedded vision systems, in: Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05), vol. 3, San Diego, California, USA, June 2005, p. 131.
2. R.J. Petersen, B.L. Hutchings, An assesment of the suitability of FPGA-based systems for use in digital signal processing, in: 5th International Workshop on Field-Programmable Logic and Applications, Oxford, England, August 1995, pp. 293-302.
3. Draper B.A., Beveridge J.R., Bohm A.P.W., Ross Ch., and Chawath M. Accelerated image processing on FPGAs. IEEE Transactions on Image Processing 12 12 (2003)
4. M.A. Vega-Rodriguez, J.M. Sanchez-Perez, J.A. Gomez-Pulido, Real time image processing with reconfigurable hardware, in: 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS2001), vol. 1, Malta, September 2001, pp. 213-216.
5. M. Leeser, S. Miller, H. Yu, Smart camera based on reconfigurable hardware enables diverse real time applications, in: Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2004), Napa, CA, USA, 2004, pp. 147-155.
6. Uzun I.S., Amira A., and Bouridane A. FPGA implementations of fast fourier transforms for real time signal and image processing. IEE Proceedings-Vision, Image and Signal Processing 152 3 (2005) 283-296
7. N. Shirazi, P.M. Athanas, A.L. Abbot, Implementation of a 2D fast fourier transform on a FPGA-based custom computing machine, in: Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications, vol. 975 of Lecture Notes in Computer Science, Oxford, UK, August-September 1995, pp. 282-292.
8. M. Rogers, M. Won, A. Soohoo, Altera FPGA co-processors accelerate the performance of 3-D stereo image processing, Altera Corporation, News & Views Spring/Summer 2005.
9. Altera Corporation Home-page: .
10. National Instruments Corporation Home-page: .
11. Edge Detection Using SOPC Builder and DSP Builder Tool Flow, Altera Technical Paper, AN-377-1.0, May 2005.
12. Avalon Interface Specification, Altera Technical Paper MNL-AVABUSREF-3.1, 2005.
13. Quartus II Handbook vol. 4, p. 8 (Chapter 9), Altera Technical Paper QII54007-5.1.0, 2005.
14. Nios II Hardware Development, Altera Technical Paper TU-N2HWDV-2.0, 2005.
15. System Level Solutions Corporation Home-page: .
16. Nios II Software Developer's Handbook, NII5V2-5.0, Altera, May 2005.
17. Brown M.Z., Burschka D., and Hager G.D. Advances in computational stereo. IEEE Transactions on Pattern Analysis and Machine Intelligence 25 8 (2003) 993-1008
18. Video and Image Processing Design using FPGAs, Altera White Paper WP-VIDEO 0306-1.1, March 2007.
19. Alzahrani F.M., and Chen T. A real-time edge detector: algorithm and VLSI architecture. Real-Time Imaging 3 (1997) 363-378
20. Andreadis I., Stavroglou K., and Tsalidis Ph. Design and implementation for an ASIC for real-time manipulation of digital colour images. Microprocessors and Microsystems 19 5 (1995) 247-253
21. Doswald D., Halfiger J., Blessing O., Felber N., Niederer P., and Fichtner W. A 30-frames/sec megapixel real-time CMOS image processor. IEEE Journal of Solid State Circuits 35 11 (2000) 1732-1743
22. Soon I.Y., Yeo C.K., and Ng H.C. An analogue video interface for general-purpose DSP. Microprocessors and Microsystems 25 (2001) 33-39
23. Tenze L., Carrato S., and Olivieri S. Design and real-time implementation of a low-cost noise reduction system for video applications. Signal Processing 84 (2004) 453-466
24. OpenCore plus Evaluation of Megafunctions, Altera Technical Paper AN-320-1.3, 2005.
25. Ratha N.K., and Jain A.K. Computer vision algorithms on reconfigurable logic arrays. IEEE Transactions on Parallel and Distributed Systems 10 1 (1999) 29-43
26. A. Darabiha, J. Rose, W.J. MacLean, Video-rate stereo depth measurement on programmable hardware, in: Proceedings of the 2003 IEEE Computer Society Conference on Computer Vision & Pattern Recognition, vol. 1, Madison, WI, USA, June 2003, pp. 203-210.
27. T. Kanade, A. Yoshida, K. Oda, H. Kano, M. Tanaka, A stereo machine for video-rate dense depth mapping and its new applications, in: Proceedings of the 15th IEEE Computer Vision and Pattern Recognition Conference (ICVPR'96), San Francisco, June 1996, pp. 196-202.
28. J. Diaz, E. Ros, S. Mota, E. Ortigosa, B. Del Pino, High performance stereo computation architecture, International Conference on Field Programmable Logic and Applications, Tampere, Finland, August 2005, pp. 463-468.
29. Hall T.S. A framework for teaching real-time digital signal processing with field-programmable gate-arrays. IEEE Transactions on Education 48 3 (2005) 551-558