A multi-chip implementation of cortical orientation hypercolumns

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2004, Pages

  Choi, Thomas Y W ^a   Shi, Bertram E ^a   Boahen, Kwabena A ^b  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HYPERCOLUMNS; MULTIPLE CHIPS; ROUTING; SPIKE TRAINS;

ARRAYS; FEEDBACK; NETWORK PROTOCOLS; NETWORKS (CIRCUITS); SIGNAL PROCESSING; SILICON; TUNING;

MICROPROCESSOR CHIPS;

EID: 4344647201     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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