A high speed ASIC implementation of the Rijndael Algorithm

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Sever, Refik ^a   Ismailoǧlu, A Neslin ^a   Tekmen, Yusuf C ^a   Aşkar, Murat ^a  

^a MIDDLE EAST TECHNICAL UNIVERSITY   (Turkey)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK CYCLE; DATA ENCRYPTION STANDARD (DES); RIJNDAEL PROCESSOR;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CRYPTOGRAPHY; DATA COMMUNICATION SYSTEMS; DATA PROCESSING; FEEDBACK; MULTIPLEXING; OPTIMIZATION; VLSI CIRCUITS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 4344627819     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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2. "Draft FIPS for the AES," available from: http://csrc.nist.gov/ encryption.aes, February 2001.
3. National Institute of Standards and Technology http://csrc.nist.gov/
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6. I. Verbauwhede, P. Schaumont and H. Kuo, "Design and Performance Testing of a 2.29-GB/s Rijndael Processor," IEEE Journal of Solid State Circuits, Vol. 38, No. 3, March 2003, pp. 569-572.
7. rd AES Candidate Conference, pp. 279-285, New York, April 2000.
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11. J. H. Shim, D. W. Kim, Y. K. Kang, T.W. Kwon and J. R. Choi, "A Rijndael Cryptoprocessor Using Shared On-the-fly Key Scheduler,"available: www.ap-asic.org/2002/proceedings/2B/2B-3.PDF
12. R. Karri, K. Wu, P. Mishra, and Y. Kim, "Concurrent Error Detection Schemes for Fault-Based Side-Channel Cryptanalysis of Symmetric Block Ciphers," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, No. 12, Dec. 2002.