Supervised learning in a two-input analog floating-gate node

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2004, Pages

  Dugger, Jeff ^a   Hasler, Paul ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR VOLTAGE SIGNALS; FLOATING GATE NODE; LEAST MEAN SQUARE (LMS); SOURCE FOLLOWER FLOATING GATE (SFFG);

ALGORITHMS; COMPUTATIONAL COMPLEXITY; ELECTRIC POTENTIAL; ERROR ANALYSIS; LEARNING SYSTEMS; NETWORKS (CIRCUITS); SIGNAL PROCESSING; VECTOR QUANTIZATION;

GATES (TRANSISTOR);

EID: 4344622157     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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