A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Fan, Yongquan ^a   Zilic, Zeljko ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL EMULATORS; COMMUNICATION CHANNELS;

CHANNEL CAPACITY; COMMUNICATION SYSTEMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; MATHEMATICAL MODELS; THEOREM PROVING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 4344602224     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. M. Courtoy, "Rapid System Prototyping for Real-time Design Validation," Proc. Ninth International Workshop on Rapid System Prototyping, pp. 108-112, 1998.
3. P. Atiniramit, Design and implementation of an FPGA-based adaptive filter single-use receiver, Master Thesis, Department of Electrical Engineering, Virginia Polytechnic Institute and State University, 1999
4. A. Gazel, E. Boutillon, J.L. Danger, G. Gulak, "Design and performance analysis of a high speed AWGN communication channel emulator", IEEE PACRIM conference, Victoria, B.C., Canada, Aug. 2001
5. MSS Corporation, AWGN Generator Specification, Gaithersburg, Maryland, USA, 2002
6. S. Wolfram, "Random Sequence Generation by Cellular Automata," Advances in Applied Mathematics, vol. 7, pp. 123-169, June 1986
7. J. Chen, J. Moon and K. Bazargan, "A Reconfigurable FPGA-based Readback Signal Generator for Hard-drive Read Channel Simulator", Proc. of 39th Design Automation Conference, pp. 349-354, June 2002
8. D. E. Knuth, The Art of Computer Programming, Addison-Wesley, 1998