A 39×48 general-purpose focal-plane processor array integrated circuit

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2004, Pages

  Dudek, Piotr ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ELECTRIC POWER UTILIZATION; IMAGE PROCESSING; INTEGRATED CIRCUIT LAYOUT; PHOTODETECTORS;

CHIP ARCHITECTURES; FOCAL-PLANE PROCESSORS; PIXEL-PER-PROCESSOR ARRAYS; SINGLE INSTRUCTION MULTIPLE DATA (SIMD);

MICROPROCESSOR CHIPS;

EID: 4344586276     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. M.Ishikawa et. al. "A CMOS Vision Chip with SIMD Processing Element Array for 1ms Image Processing", Proc. ISSCC'99, TP 12.2, 1999.
2. 2 silicon area for a digital retina", Proc. SPIE, vol. 3410, AFPAEC'98. 1998.
3. G. Liñán-Cembrano et al. "A Processing Element Architecture for High-Density Focal-Plane Analog Programmable Array Processor Arrays", Proc. ISCAS 2002, vol.III, pp.341-344, May 2002.
4. P.Dudek and P.J.Hicks, "An Analogue SIMD Focal Plane Processor Array", IEEE International Symposium on Circuits and Systems, ISCAS 2001, vol.IV, pp.490-493, May 2001.
5. P.Dudek, "A Processing Element for an Analogue SIMD Vision Chip", Proc. European Conference on Circuit Theory and Design, ECCTD'03, vol.III, pp.221-224, September 2003.
6. P.Dudek, "A Flexible Global Readout Architecture for an Analogue SIMD Vision Chip", Proc. ISCAS 2003, May 2003.
7. J.-S. Wang and C.-L. Wey, "Accurate CMOS Switched-Current Divider Circuits", Proc. ISCAS'98, vol I, pp.53-56, May 1998.