Patterning techniques for next generation ICs

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6798, Issue , 2008, Pages

  Balasinski, A ^a  

^a CYPRESS SEMICONDUCTOR   (United States)

Author keywords

Design for manufacturability; Double patterning; Extreme UV; Inverse lithography; Nanoimprint

Indexed keywords

ETCHING; NANOIMPRINT LITHOGRAPHY; RISK ANALYSIS; WAFER BONDING;

DESIGN FOR MANUFACTURABILITY; DOUBLE PATTERNING TECHNIQUE (DPT); INVERSE LITHOGRAPHY; MARKET AVAILABILITY;

INTEGRATED CIRCUITS;

ELECTRIC CIRCUITS; ETCHING; LITHOGRAPHY; RISK ASSESSMENT;

EID: 43249127002     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.758963     Document Type: Conference Paper

References (5)

1. SPIE/Microlithography Conference Panel Discussion, P.Luehrmann (moderator), DPT: Twice the Pain for Twice the Gain, San Jose, Feb. 28, 2007.
2. BACUS/Photomask Conference Special Session, Hiroichi Kawahira, Chair, Monterey, CA, Sept. 21, 2007.
3. A. Poonawala, Y. Borodovsky, P. Milanfar, ILT for Double-exposure Lithography with Conventional and Novel Materials, Proc. SPIE, vol. 6520, March 2007.
4. I.Borodovsky, Proc. SPIE/Microlithography Conference, vol. 6153, Feb. 22, 2006.
5. M.Levinson, Doubling Down at BACUS, Microlithography World, November 2007.