Systematic yield estimation method applying lithography simulation

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6925, Issue , 2008, Pages

  Kyoh, Suigen ^a   Inoue, Soichi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Design for manufacturability; Layout optimization; Systematic yield estimation

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; SILICON WAFERS;

DESIGN FOR MANUFACTURABILITY; LAYOUT OPTIMIZATION; SYSTEMATIC YIELD ESTIMATION;

LITHOGRAPHY;

EID: 43249093215     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.772747     Document Type: Conference Paper

References (4)

1. T. Kotani et al, "Yield enhanced layout generation by new design for manufacturability," Proc. SPIE 5379, (2003)
2. S. Inoue, "Patterning friendly design methodology for 65nm and beyond technology nodes," 8th International Forum on Semiconductor Technology IFST, (2005)
3. S. Inoue et al, "Total hot spot management from design rule definition to silicon fabrication," Electronic Design Processes Workshop EDP, (2003)
4. Charles H. Stapper et al, "Integrated Circuit Yield Management and Yield Analysis: Development and Implementation," IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 8, NO. 2, 95-102 (1995)