IP core design of PLC microprocessor with boolean module

2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, HDP'05

Volumn , Issue , 2006, Pages

  Xu, Mei Hua ^a   Ran, Feng ^a   Chen, Zhang Jin ^a   Kang, Shu Feng ^a   Li, Run Guang ^a  

^a SHANGHAI UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER PROGRAMMING LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAMMABLE LOGIC CONTROLLERS;

BOOLEAN PROCESSOR; INTERNATIONAL STANDARDS; MICROPROCESSOR IP CORE; SYSTEMATIC DESIGN REQUIREMENTS;

MICROPROCESSOR CHIPS;

EID: 42749107646     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HDP.2005.251460     Document Type: Conference Paper

References (4)

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2. Wasserman, Y, "Integrated Single-Wafer RP Solutions for 0.25-micron Technologies," IEEE Trans-CPMT-A, Vol. 17, No. 3 (1995), pp. 346-351. [A reference to a journal article ...]
3. th Electronic Components and Technology Conf, Orlando, FL, May. 1996, pp. 219-225. [A reference to a presentation at a Conference...]
4. K.H. John and M.Tiegelkamp. SPS-Programmierung mit TEC 61131-3, Springer Berlin Heidelberg New York, 1999, 3rd Ed. (German), ISBN 3-540-66445-9