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Volumn , Issue , 2007, Pages 683-688

A dual-use snubber design for multi-level inverter systems

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; POWER CONVERTERS; PRODUCT DESIGN; SEMICONDUCTOR DEVICES;

EID: 42549163013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPEMC.2006.283241     Document Type: Conference Paper
Times cited : (7)

References (6)
  • 4
    • 0000645093 scopus 로고
    • Efficient snubbers for voltage-source inverters
    • July
    • W. McMurray, "Efficient snubbers for voltage-source inverters, "IEEE Trans., Power Electronics". Vol. PE-2, no 3, pp 264-274 July 1987.
    • (1987) IEEE Trans., Power Electronics , vol.PE-2 , Issue.3 , pp. 264-274
    • McMurray, W.1
  • 5
    • 33947688933 scopus 로고
    • Switching Stress Reduction in Power Transistor Inverter
    • Tore M. Undeland, "Switching Stress Reduction in Power Transistor Inverter", IEEE Industrial, 1976.
    • (1976) IEEE Industrial
    • Undeland, T.M.1
  • 6
    • 33947686914 scopus 로고    scopus 로고
    • A simple snubber configuration for three level voltage source GTO inverters
    • Joonmi OH, Jinhwang Jung and Kwanghee Nam," A simple snubber configuration for three level voltage source GTO inverters", 0-7803-3008-0/95$4.00 ©1995 IEEE.
    • 0-7803-3008-0/95$4.00 ©1995 IEEE
    • Joonmi, O.H.1    Jung, J.2    Nam, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.