An optimized snubber design for three level inverter systems

2005 European Conference on Power Electronics and Applications

Volumn 2005, Issue , 2005, Pages

  Al Nasseir, J ^a   Weindl, Gh ^a   Herold, G ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

Converter circuit; FACTS; Power semiconductor device; Protection device; Voltage source converter

Indexed keywords

COMPUTER SIMULATION; ELECTRIC LOSSES; ELECTRIC POWER TRANSMISSION; POWER CONVERTERS; SEMICONDUCTOR DEVICES;

CONVERTER CIRCUITS; FLEXIBLE AC TRANSMISSION SYSTEMS (FACTS); POWER SEMICONDUCTOR DEVICE; PROTECTION DEVICE; SNUBBER; VOLTAGE SOURCE CONVERTER;

ELECTRIC INVERTERS;

EID: 33947616169     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. th International Power Electronic and Motion Control Conference. Sep, 2-4 Riga, Latvia 2004.
2. Ned Mohan, Tore M. Undeland, William P. Robins, Power electronic; second edition, John Wiley & Sons Inc New York, USA, 1955.
3. W. McMurray "Efficient snubbers for voltage-source inverters, "IEEE Trans., Power Electronics". Vol. PE-2, no 3, pp 264-274 July 1987.
4. Tore M. Undeland, "Switching Stress Reduction in Power Transistor Inverter", IEEE Industrial, 1976.
5. Tore M. Undeland, F. Jensen, A. Steinbakk, T. Rogne, and M. Hernes," A snubber configuration for both power transistor and GTO PWM Inverter;" IEEE Power Electronics Specialist Conf. Rec., Gaithersberg, MD, June 18-21, 1984, pp. 42-53.
6. Joonmi OH, Jinhwang Jung and Kwanghee Nam," A simple snubber configuration for three level voltage source GTO inverters", 0-7803-3008-0/95$4.00 ©1995 IEEE.