UIS-failure of DMOS power transistors

European Solid-State Device Research Conference

Volumn , Issue , 2002, Pages 459-462

  Icazs Deckelmann, A ^a   Wachutka, G ^a   Hirler, F ^b   Krumrey, J ^b  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

TRANSISTORS;

ELECTROTHERMAL DEVICES; FAILURE CONDITIONS; FAILURE MECHANISM; PLAUSIBLE MODEL; POWER TRANSISTORS; UNCLAMPED INDUCTIVE SWITCHING;

POWER ELECTRONICS;

EID: 42549088994     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2002.194967     Document Type: Conference Paper

References (5)

1. P.Hower et al., "Avalanche-induced thermal instability in Ldmos transistors", Proc. ISPSD2001 pp.153- 156.
2. D.L.Blackburn, "Power MOSFET failure revisited", PESC '88, pp.681-688.
3. D.B.M.Klaassen, "An unified mobiliy model for device simulation", Proc. IEDM '90, pp.357-360.
4. S.M.Sze, Physics of Semiconductor Devices, John Wiley & Sons, New York, 1981.
5. H.S.Carslaw, J.C.Jaeger, Conduction of Heat in Solids, Oxford University Press, 1959