A novel parasitic-aware synthesis and verification flow for RFIC desien

Proceedings of the 36th European Microwave Conference, EuMC 2006

Volumn , Issue , 2006, Pages 664-667

  Xuejin, Wang ^a   McCracken, Stephen ^a   Dengi, Aykut ^a   Takinami, Koji ^b   Tsukizawa, Takayuki ^b   Miyahara, Yasunori ^b  

^a Cadence Design Systems Inc   (United States)

^b PANASONIC CORPORATION   (Japan)

Author keywords

Circuit optimization; Circuit synthesis; Electromagnetic analysis; Integrated circuit interconnections; Voltage controlled oscillators

Indexed keywords

CONVERGENCE OF NUMERICAL METHODS; ELECTROMAGNETIC WAVES; INTERCONNECTION NETWORKS; ITERATIVE METHODS; VARIABLE FREQUENCY OSCILLATORS;

CIRCUIT OPTIMIZATION; CIRCUIT SYNTHESIS; ELECTROMAGNETIC ANALYSIS; INTEGRATED CIRCUIT INTERCONNECTIONS;

INTEGRATED CIRCUITS;

EID: 41649101830     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EUMC.2006.281498     Document Type: Conference Paper

References (7)

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