Modeling and mitigation of jitter in high-speed source-synchronous inter-chip communication systems

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2003, Pages 1681-1687

  Balamurugan, Ganesh ^a   Shanbhag, Naresh ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK-DATA RECOVERY (CDR); INTER-CHIP COMMUNICATION; JITTER AMPLIFICATION; JITTER EQUALIZATION;

AMPLIFICATION; COMMUNICATION CHANNELS (INFORMATION THEORY); DATA COMMUNICATION SYSTEMS; MICROPROCESSOR CHIPS; SIGNAL INTERFERENCE; SYNCHRONIZATION; TELECOMMUNICATION LINKS;

JITTER;

EID: 4143082962     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. A. Martin et al., "8 Gb/s differential simultaneous bidirectional link with 4mV 9ps waveform capture diagnostic capability," Proceedings of ISSCC, 2003, pp. 78-79, 2003.
2. J. Zerbe et al., "Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell," Proceedings of ISSCC, 2003, pp. 80-81, 2003.
3. E. A. Lee and D. G. Messerschmitt, Digital Communication. Kluwer Academic Publishers, 1994.
4. E. Yeung et al., "A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation," IEEE Journal of Solid-State Circuits, pp. 1619-1628, November 2000.
5. A. Hajimiri, "Noise in phase-locked loops," Southwest Symposium on Mixed-Signal Design, 2001 (SSMSD), pp. 1-6, 2001.
6. R. Farjad-Rad et al., "A 0.3-μm cmos 8-Gb/s 4-PAM serial link transceiver," IEEE Journal of Solid-State Circuits, pp. 757-764, May 2000.
7. P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition. John Wiley & Sons, Inc., 2001.
8. S. Haykin, Adaptive Filter Theory. Prentice-Hall Inc., 1996.
9. J. Proakis and D. Manolakis, Digital Signal Processing, 3rd Edition. Prentice-Hall Inc., 1996.