A 0.18 μm 4 Mbit toggling MRAM

2004 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2004, Pages 27-30

  Durlam, M ^a   Addie, D ^a   Akerman, J ^a   Butcher, B ^a   Brown, P ^a   Chan, J ^a   Deherrera, M ^a   Engel, B N ^a   Feil, B ^a   Grynkewich, G ^a   Janesky, J ^a   Johnson, M ^a   Kyler, K ^a   Molla, J ^a   Martin, J ^a   Nagel, K ^a   Nahas, J ^b   Ren, J ^a   Rizzo, N D ^a   Rodriguez, T ^a   Savtchenko, L ^a   Salter, J ^a   Slaughter, J M ^a   Smith, K ^a   Sun, J J ^a   Lien, M ^a   Papworth, K ^a   Shah, P ^a   Qin, W ^a   Williams, R ^a   Wise, L ^a   Tehrani, S ^a   more..

^a MOTOROLA INC   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MAGNETIC SWITCHING; MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM); SPIN POLARIZATION; TUNNEL BARRIERS;

ANTIFERROMAGNETIC MATERIALS; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; MAGNETIC STORAGE; MAGNETORESISTANCE; SWITCHING; TRANSISTORS;

RANDOM ACCESS STORAGE;

EID: 4143054818     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M. Durlam, et al., 2002 Symposium on VLSI circuits, IEEE, 158-161, June 2002.
2. L. Savtchenko, et al., "Method of writing to scalable magnetoresistance random access memory element," US patent 6,545,906 Bl, 8 April 2008.
3. S. Tehrani, et al., "Magnetoresistive Random Access Memory Using Magnetic Tunnel Junctions", Proceedings of the IEEE, 703-714, May 2003.
4. M. Durlam, et al., "A 0.18μm 4Mb Toggling MRAM," 2003 International Electron Devices Meeting, IEEE, paper 34.6, December 2003
5. J. Nahas, et al., "A 4 Mbit 0.18 μm 1T1MTJ "Toggle" MRAM Memory," 2004 International Solid State Circuits Conference, paper 2.3, February 2004.