IP integration overhead analysis in system-on-chip video encoder

Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Volumn , Issue , 2007, Pages 333-336

  Rasmus, Antti ^a   Kulmala, Ari ^a   Salminen, Erno ^a   Hämäläinen, Timo D ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; CUSTOMER SATISFACTION; ELECTRIC NETWORK TOPOLOGY; ELECTRON TUBES; INTEGRATED CIRCUITS; INTEGRATION; INTERNET PROTOCOLS; MICROPROCESSOR CHIPS; MOTION PICTURE EXPERTS GROUP STANDARDS; NETWORK ARCHITECTURE; NETWORKS (CIRCUITS); PROGRAMMABLE LOGIC CONTROLLERS; WIRELESS NETWORKS;

BLACK BOXES; CASE STUDIES; CLOCK CYCLES; CURRENT SYSTEMS; DATA DELIVERY; ELECTRONIC CIRCUITS; EXECUTION TIME; HARDWARE ACCELERATORS; INTELLECTUAL PROPERTY BLOCK (IP BLOCK); IP INTEGRATION; MULTI PROCESSOR SYSTEM ON CHIP (MP SOC); ON CHIP NETWORK (OCN); RESOURCE CONTENTION; RUN TIME; SYSTEM ON CHIP (SOCS); VIDEO ENCODERS;

ACCELERATION;

EID: 41149149970     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2007.4295306     Document Type: Conference Paper

References (9)

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