Analysis of a passive sensor for predicting process-induced stress in advanced integrated circuit interconnect

IEEE Transactions on Device and Materials Reliability

Volumn 8, Issue 1, 2008, Pages 174-181

  Gallacher, Barry J ^b   O'Neill, Anthony G ^a,b   Bull, Steve J ^b   Wilson, Christopher J ^a,b   Horsfall, Alton B ^b  

^a IEEE

^b NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

Interconnect; Reliability; Strain; Stress

Indexed keywords

FAILURE ANALYSIS; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; RELIABILITY ANALYSIS; STRAIN; STRESS MEASUREMENT;

ANALYTICAL MODEL; INTERCONNECT RELIABILITY; INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS; PASSIVE STRAIN SENSORS;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 40549090956     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2007.912272     Document Type: Article

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