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Volumn , Issue , 2006, Pages 772-778

Stepping forward with interpolates in unbounded model checking

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; BOOLEAN FUNCTIONS; DESIGN;

EID: 40549089117     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320119     Document Type: Conference Paper
Times cited : (22)

References (17)
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    • M. Sheeran, S. Singh, and G. Stålmarck, Checking Safety Properties Using Induction and SAT Solver. In W. A. Hunt and S. D. Johnson, editors, Proc. Formal Methods in Computer-Aided Design, volume 1954 of LNCS, pages 108-125. Springer-Verlag, November 2000.
    • (2000) LNCS , vol.1954 , pp. 108-125
    • Sheeran, M.1    Singh, S.2    Stålmarck, G.3
  • 2
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    • Applying SAT Methods in Unbounded Symbolic Model Checking
    • and, editors, Copenhagen, Denmark
    • K. L. McMillan. Applying SAT Methods in Unbounded Symbolic Model Checking. In Ed Brinksma and Kim Guldstrand Larsen, editors, Proc. Computer Aided Verification, volume 2404 of LNCS, pages 250-264, Copenhagen, Denmark, 2002.
    • (2002) Proc. Computer Aided Verification, volume 2404 of LNCS , pp. 250-264
    • McMillan, K.L.1
  • 3
    • 16244414873 scopus 로고    scopus 로고
    • Efficient SAT-based Unbounded Symbolic Model Checking Using Circuit Cofactoring
    • San Jose, California, November
    • M. K. Ganai, A. Gupta, and P. Ashar. Efficient SAT-based Unbounded Symbolic Model Checking Using Circuit Cofactoring. In Proc. Int'l Conf. on Computer-Aided Design, San Jose, California, November 2004.
    • (2004) Proc. Int'l Conf. on Computer-Aided Design
    • Ganai, M.K.1    Gupta, A.2    Ashar, P.3
  • 4
    • 33745162025 scopus 로고    scopus 로고
    • Interpolation and SAT-Based Model Checking
    • Warren A. Hunt Jr. and Fabio Somenzi, editors, Proc. Computer Aided Verification, of, Boulder, CO, USA
    • K. L. McMillan. Interpolation and SAT-Based Model Checking. In Warren A. Hunt Jr. and Fabio Somenzi, editors, Proc. Computer Aided Verification, volume 2725 of LNCS, pages 1-13, Boulder, CO, USA, 2003.
    • (2003) LNCS , vol.2725 , pp. 1-13
    • McMillan, K.L.1
  • 5
    • 33646386898 scopus 로고    scopus 로고
    • Improvements to the implementation of Interpolant-Based Model Checking
    • D. Borrione and W. Paul, editors, Proc. Computer Aided Verification, of, Edimburgh, Scotlan, UK
    • J. Marque-Silva. Improvements to the implementation of Interpolant-Based Model Checking. In D. Borrione and W. Paul, editors, Proc. Computer Aided Verification, volume 3725 of LNCS, pages 367-370, Edimburgh, Scotlan, UK, 2005.
    • (2005) LNCS , vol.3725 , pp. 367-370
    • Marque-Silva, J.1
  • 7
  • 9
    • 84948155079 scopus 로고    scopus 로고
    • Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis
    • M. D. Aagaard and J. W. O'Leary, editors, Proc. Formal Methods in Computer-Aided Design, of, November
    • P. Chauhan, E. Clarke, J. Kukula, S. Sapra, H. Veith, and D. Wang. Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis. In M. D. Aagaard and J. W. O'Leary, editors, Proc. Formal Methods in Computer-Aided Design, volume 2517 of LNCS, pages 35-51, November 2002.
    • (2002) LNCS , vol.2517 , pp. 35-51
    • Chauhan, P.1    Clarke, E.2    Kukula, J.3    Sapra, S.4    Veith, H.5    Wang, D.6
  • 10
    • 0036576020 scopus 로고    scopus 로고
    • Search Pruning Techniques in SAT-based Branch-and-Bound Algorithms for the Binate Covering Problem
    • V. Manquinho and J. Marques-Silva. Search Pruning Techniques in SAT-based Branch-and-Bound Algorithms for the Binate Covering Problem. IEEE Trans. on Computer-Aided Design, 21:505-516, 2002.
    • (2002) IEEE Trans. on Computer-Aided Design , vol.21 , pp. 505-516
    • Manquinho, V.1    Marques-Silva, J.2
  • 11
    • 26944433552 scopus 로고    scopus 로고
    • Efficient and Effective Redundancy Removal for Million-Gate Circuits
    • Paris, Prance, March
    • M. Berkelaar and K. van Eijk. Efficient and Effective Redundancy Removal for Million-Gate Circuits. In Proc. Design Automation & Test in Europe Conf., pages 1088-1088, Paris, Prance, March 2002.
    • (2002) Proc. Design Automation & Test in Europe Conf , pp. 1088-1088
    • Berkelaar, M.1    van Eijk, K.2
  • 12
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    • Scalable Logic Synthesis using a Simple Circuit Structure
    • Lake Tahoe, California, May
    • A. Mishchenko and R. K. Brayton. Scalable Logic Synthesis using a Simple Circuit Structure. In Proc. Int'l Workshop on Logic Synthesis, Lake Tahoe, California, May 2006.
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  • 15
    • 33646941293 scopus 로고    scopus 로고
    • Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking
    • Munich, Germany, March
    • G. Cabodi, S. Nocco, and S. Quer. Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking. In Proc. Design Automation & Test in Europe Conf., Munich, Germany, March 2005.
    • (2005) Proc. Design Automation & Test in Europe Conf
    • Cabodi, G.1    Nocco, S.2    Quer, S.3
  • 17
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    • IBM Formal Verification Benchmark Library
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.