CMP model based RC extraction

2007 International Symposium on Integrated Circuits, ISIC

Volumn , Issue , 2007, Pages 532-535

  Liao, Hongmei ^a   Song, Li ^b   Jakatdar, Nickhil ^b   Radojcic, Riko ^a  

^a QUALCOMM INC   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC COMPOUNDS; CHEMICAL POLISHING; COMPUTER NETWORKS; INDUSTRIAL ENGINEERING; INTEGRATED CIRCUITS; LITHOGRAPHY; PROCESS ENGINEERING; TIME MEASUREMENT;

CMP PROCESSES; THICKNESS VARIATIONS;

NANOTECHNOLOGY;

EID: 40349113925     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISICIR.2007.4441916     Document Type: Conference Paper

References (5)

1. White, D. and A. Gower, "Impact of Multi-Level Chemical Mechanical Polishing on 90 nm and Below", (invited paper), 22nd International VLSI/ULSI Multilevel Interconnect Conference, October 2005.
2. Borst, C., S. Smith, and M. Eissa, "Challenges and Rewards of Low-abrasive Copper CVP: Evaluation and Integration for Single-Damascene Cu/Low-k Interconnects for the 90nm Node," MRS Spring Meeting, San Francisco, 2004.
3. N.D. Arora and L. Song, "Modeling and Characterization of High Frequency Effects in ULSI Interconnects", Proc. NSTI Nanotech WCM 2005, pp46-51.
4. N.D. Arora, L. Song, S. Shah, K. Thumaty, A. Fujimura, L.C. Yeh and P. Yang, "Interconnect Characterization of X Architecture Diagonal Lines for VLSI Design", IEEE J. Semiconductor Manufacturing, Vol 18, pp. 262-270, May, 2005.
5. N. D. Arora and L. Song, "Atto-farad Measurement and Modeling of on-chip Coupling Capacitance", IEEE Electron Device Letter, vol. 25, pp.92-94, No. 2, 2004.