Interconnect characterization of X architecture diagonal lines for VLSI design

IEEE Transactions on Semiconductor Manufacturing

Volumn 18, Issue 2, 2005, Pages 262-270

  Arora, Narain D ^a   Song, Li ^a   Shah, Santosh M ^a   Joshi, Ketan ^a   Thumaty, Kalyan ^a   Fujimura, Aki ^a   Yeh, L C ^b   Yang, Ping ^c  

^a CADENCE DESIGN SYSTEMS   (United States)

^b Manufacturing Corp   (Taiwan)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Interconnect characterization; Interconnect process parameters; Interconnect test structures; X Architecture

Indexed keywords

CAPACITANCE; DIELECTRIC PROPERTIES; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT MANUFACTURE; LARGE SCALE SYSTEMS; MASKS; MICROPROCESSOR CHIPS; WIRE; X RAY LITHOGRAPHY;

INTERCONNECT CHARACTERIZATION; INTERCONNECT PARAMETERS; INTERCONNECT TEST STRUCTURES; X ARCHITECTURE;

VLSI CIRCUITS;

CAPACITANCE; CHIPS; DIELECTRIC PROPERTIES; ELECTRIC RESISTANCE; MASKING;

EID: 19544385973     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2005.845037     Document Type: Conference Paper

References (8)

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