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Volumn 44, Issue 5, 2008, Pages 349-351

Implementing ultra-high-value floating tunable CMOS resistors

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CUTOFF FREQUENCY; ELECTRIC FILTERS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES;

EID: 40149099350     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20082538     Document Type: Article
Times cited : (101)

References (6)
  • 1
    • 18744397570 scopus 로고    scopus 로고
    • Linearisation of MOS resistors using capacitive gate voltage averaging
    • 10.1049/el:20050565 0013-5194
    • Ramirez-Angulo, J., Sawant, M.S., Carvajal, R.G., and Lopez-Martin, A.: ' Linearisation of MOS resistors using capacitive gate voltage averaging ', Electron. Lett., 2005, 41, (9), p. 511-512 10.1049/el:20050565 0013-5194
    • (2005) Electron. Lett. , vol.41 , Issue.9 , pp. 511-512
    • Ramirez-Angulo, J.1    Sawant, M.S.2    Carvajal, R.G.3    Lopez-Martin, A.4
  • 2
    • 34047174942 scopus 로고    scopus 로고
    • Sub-threshold R-MOSFET tunable resistor technique
    • 10.1049/el:20070175 0013-5194
    • Worapishet, A., and Khumsat, P.: ' Sub-threshold R-MOSFET tunable resistor technique ', Electron. Lett., 2007, 43, (7), p. 390-392 10.1049/el:20070175 0013-5194
    • (2007) Electron. Lett. , vol.43 , Issue.7 , pp. 390-392
    • Worapishet, A.1    Khumsat, P.2
  • 3
    • 34548027940 scopus 로고    scopus 로고
    • Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device
    • 0013-5194
    • Tajalli, A., Vittoz, E., Leblebici, Y., and Brauer, E.J.: ' Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device ', Electron. Lett., 2007, 43, (17), p. 911-913 0013-5194
    • (2007) Electron. Lett. , vol.43 , Issue.17 , pp. 911-913
    • Tajalli, A.1    Vittoz, E.2    Leblebici, Y.3    Brauer, E.J.4
  • 4
    • 34249980397 scopus 로고    scopus 로고
    • Bulk-drain connected load for subthreshold MOS current-mode logic
    • 10.1049/el:20070370 0013-5194
    • Cannillo, F., Toumazou, C., and Lande, T.S.: ' Bulk-drain connected load for subthreshold MOS current-mode logic ', Electron. Lett., 2007, 43, (12), p. 662-664 10.1049/el:20070370 0013-5194
    • (2007) Electron. Lett. , vol.43 , Issue.12 , pp. 662-664
    • Cannillo, F.1    Toumazou, C.2    Lande, T.S.3
  • 5
    • 0029342165 scopus 로고
    • An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications
    • 0925-1030
    • Enz, C.C., Krummenacher, F., and Vittoz, E.A.: ' An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications ', Analog Integr. Circuits Signal Process., 1995, 5, p. 83-114 0925-1030
    • (1995) Analog Integr. Circuits Signal Process. , vol.5 , pp. 83-114
    • Enz, C.C.1    Krummenacher, F.2    Vittoz, E.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.