A 512×8 electrical fuse memory with 15μm2 cells using 8-sq asymmetric fuse and core devices in 90nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 74-75

  Chung, Shine ^a   Huang, Jiann Tseng ^a   Chen, Paul ^a   Hsueh, Fu Lung ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; RELIABILITY; STORAGE ALLOCATION (COMPUTER);

ASYMMETRIC FUSE; ELECTRICAL FUSE MEMORY; SUFFICIENT DESIGN WINDOW;

CMOS INTEGRATED CIRCUITS;

EID: 39749199474     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342771     Document Type: Conference Paper

References (2)

1. M. Alavi et. al., "A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process," IEDM Digest of Technical Papers, pp855-858, Dec., 1997.
2. S. Kothandaraman et. al., "Electrically Programmable Fuse Using Electromigration in Suicides," IEEE J. Solid State Circuits, Vol. 23, No. 9, pp523-525, Dec., 2002.