Design and FPGA implementation of a pseudo-random bit sequence generator using spatiotemporal chaos

2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings

Volumn 3, Issue , 2006, Pages 2114-2118

  Mao, Yaobin ^a   Cao, Liu ^a   Liu, Wenbo ^b  

^a NANJING UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

^b NANJING UNIVERSITY OF AERONAUTICS AND ASTRONAUTICS   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CHAOTIC SYSTEMS; COMPUTER SIMULATION; CRYPTOGRAPHY; LARGE SCALE SYSTEMS;

ELEMENTARY HARDWARE SIMULATION; PSEUDO-RANDOM BIT SEQUENCE (PRBS);

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 39749178885     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCCAS.2006.284916     Document Type: Conference Paper

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