1 Gbit/s bidirectional full-wire rate communication LSI for residential gateways

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 138-139

  Nishida, Yukikuni ^a   Kawai, Kenji ^a   Koike, Keiichi ^a   Oyama, Katsuichi ^a   Hayashi, Tetsuo ^a   Nouchi, Hiroyuki ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC POWER UTILIZATION; ELECTRIC WIRE;

DECRYPTION; IPSEC CIRCUIT; RESIDENTIAL GATEWAYS;

QUALITY OF SERVICE;

EID: 39749177850     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342689     Document Type: Conference Paper

References (6)

1. M P. Goetz, et al., "COST/PERFORMANCE ANALYSIS OF HIGH PIN COUNT SURFACE MOUNT PLASTIC PACKAGES", http://wvwv.asat.conVprodu.ets/library/ bg1001.pdf.
2. T. Grembowski, et al., "Comparative Analysis of the Hardware Implementations of Hash Functions SHA-I and SHA-512", LNCS2433,pp.75-89, 2002.
3. C. S. Ha, et al., "ASIC Design of IPSec Hardware Accelerator for Network Security", AP-ASIC2004, pp.168-171, 2004.
4. H. E. Michail, et al, "EFFICIENT IMPLEMENTATION OF THE KEYED-HASH MESSAGE A UTHENTICATION CODE (HMAC) USING THE SHA-I HASH FUNCTION", ICECS'04, pp.567-570, 2004.
5. M Y. Wang, et al., "An HMAC processor with integrated SHA-I and MD5 algorithms", ASP-DAC 2004, pp.456-458, 2004.
6. M. Shreedhar, G. Varghese, "Efficient Fair Queuing using Deficit Round Robin", SIGCOMM '95, pp.231-242, 1995.