A 6.5GHz 54mW 64-bit parity-checking adder for 65nm fault-tolerant microprocessor execution cores

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 46-47

  Mathew, Sanu ^a   Anders, Mark ^a   Krishnamurthy, Ram ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; ELECTRIC POWER UTILIZATION;

FAULT TOLERANT MICROPROCESSOR; MULTI BIT OUTPUT ERRORS; PARITY COMPUTATION DELAY;

MICROPROCESSOR CHIPS;

EID: 39749116208     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342760     Document Type: Conference Paper

References (3)

1. M. Nieolaidis, IEEE Trans. On VLSI Systems, pp. 121-128. Feb. 2003.
2. S. Mathew el al, Journal of Solid State Circuits, pp 44-51, Jan 2005.
3. P. Bai et al., Proc. IEDM. pp. 657-660, Deo. 2004.