Concurrent design of delta-sigma modulator using behavioral modeling and simulation with the Verilog-A

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 341-344

  Yamamoto, Takafumi ^a   Suzuki, Tsutomu ^a   Asai, Hideki ^a  

^a SHIZUOKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; CIRCUIT SIMULATION; INTEGRATED CIRCUIT LAYOUT; TRANSISTORS;

ANALOG CIRCUIT DESIGN; CONCURRENT DESIGN;

DELTA SIGMA MODULATION;

EID: 39049159189     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320917     Document Type: Conference Paper

References (7)

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3. R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, A John Wiley & Sons, Inc.
4. S. R. Norsworthy, R. Schreier and G. C. Temes, Delta-Sigma Data Converters, A John Wiley & Sons, Inc.
5. B. Razavi. Design of Analog CMOS Integrated circuits, The McGraw-Hill companies, Inc, 2000
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7. G. M. Yin, F. Op't Eynde, and W. sansen, "A High-Speed CMOS Comparator with 8-b Resolution," IEEE Journal of Solid-State Circuits, Vol. 27, No. 2, February 1992