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Volumn , Issue , 2007, Pages 124-133

Necessary and sufficient conditions for deterministic desynchronization

Author keywords

Correctness; Desynchronization; Determinism; Endochrony; Execution machine; GALS; Kahn process network; Reaction to signal absence

Indexed keywords

DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SYSTEMS;

EID: 38849174698     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1289927.1289950     Document Type: Conference Paper
Times cited : (7)

References (15)
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    • (1995) Proceedings PLDI'95
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  • 3
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    • Benveniste, A.1    Caillaud, B.2    Guernic, P.L.3
  • 5
    • 17144475364 scopus 로고
    • The SL synchronous language
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    • F. Boussinot and R. de Simone. The SL synchronous language. Research Report RR-2510, INRIA, Sophia Antipolis, France, March 1995. http://www.inria.fr/rrrt/rr-2510.html.
    • (1995) Research Report
    • Boussinot, F.1    de Simone, R.2
  • 7
    • 84866694666 scopus 로고    scopus 로고
    • T. Grandpierre and Y. Sorel. From algorithm and architecture specification to automatic generation of distributed real-time executives: a seamless flow of graphs transformations. In Proceedings of First ACM and IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE'03, Mont Saint-Michel, France, June 2003.
    • T. Grandpierre and Y. Sorel. From algorithm and architecture specification to automatic generation of distributed real-time executives: a seamless flow of graphs transformations. In Proceedings of First ACM and IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE'03, Mont Saint-Michel, France, June 2003.
  • 11
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    • The semantics of a simple language for parallel programming
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    • Lee, E.1    Park, T.2
  • 13
    • 34547355660 scopus 로고    scopus 로고
    • Correct-by-construction asynchronous implementation of modular synchronous specifications
    • D. Potop-Butucaru and B. Caillaud. Correct-by-construction asynchronous implementation of modular synchronous specifications. Fundamenta Informaticae, 78(1):131-159, 2007.
    • (2007) Fundamenta Informaticae , vol.78 , Issue.1 , pp. 131-159
    • Potop-Butucaru, D.1    Caillaud, B.2
  • 15
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    • Generalized latency-insensitive systems for single-clock and multi-clock architectures
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    • M. Singh and M. Theobald. Generalized latency-insensitive systems for single-clock and multi-clock architectures. In Proceedings DATE'04, Paris, France, 2004.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.