Analysis of absorbing sets for array-based LDPC codes

IEEE International Conference on Communications

Volumn , Issue , 2007, Pages 6261-6268

  Dolecek, Lara ^a   Zhang, Zhengya ^a   Anantharam, Venkat ^a   Wainwright, Martin ^a   Nikolić, Borivoje ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSORBING SETS; LOW DENSITY PARITY CHECK CODES (LDPC); TANNER GRAPH;

BIT ERROR RATE; COMPUTER HARDWARE; SIGNAL TO NOISE RATIO;

ITERATIVE DECODING;

EID: 38549171376     PISSN: 05361486     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICC.2007.1037     Document Type: Conference Paper

References (10)

1. C. Di, D. Proietti, T. Richardson, E. Telatar, and R. Urbanke, "Finite length analysis of low-density parity-check codes on the binary erasure channel," IEEE Trans. Inform. Theory, vol. (48), pp. 1570-1579.
2. E. Eleftheriou and S. Ölçer, "Low density parity check codes for digital subscriber lines", Proc. of the IEEE Int. Conf. on Commun., New York, NY, 2002, pp. 1752-1757.
3. J. L. Fan, "Array-codes as low-density parity-check codes," Second Int. Symp. on Turbo Codes, Brest, France, pp. 543-46, Sept. 2000.
4. J. Feldman, M. J. Wainwright and D. R. Karger, "Using linear programming to decode binary linear codes", IEEE Trans. Inform. Theory, vol. (51), pp. 954-972.
5. G. D. Forney, "Codes on graphs: normal realizations", IEEE Trans. Inform. Theory, vol. (47), pp. 520-548, Feb. 2001.
6. D. MacKay and M. Postol, "Weaknesses of Margulis and Ramanujan-Margulis low-density parity-check codes," Elec. Notes in Theo. Comp. Sci., vol. 74, 2003.
7. T. Richardson, "Error-floors of LDPC codes," in Proc. of the 41st Annual Allerton Conference, Monticello, Ill., Oct. 2003.
8. B. Vasic and E. Kurtas, "Coding and Signal Processing for Magnetic Recording Systems", CRC press, 2005.
9. K. Yang and T. Helleseth, "On the minimum distance of array codes as LDPC codes", IEEE Trans. Inform. Theory, vol. 49(12), pp. 3268-3271, Dec. 2003.
10. Z. Zhang, L. Doleèek, B. Nikolic, V. Anantharam and M. Wainwright, "Investigation of error floors of structured low-density parity-check codes via hardware simulation", Proc. GLOBECOM 2006, San Francisco, CA, Nov.-Dec. 2006.